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Cypress Semiconductor /psoc63 /I2S0 /CLOCK_CTL

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Interpret as CLOCK_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLOCK_DIV0 (CLOCK_SEL)CLOCK_SEL

Description

Clock control

Fields

CLOCK_DIV

Frequency divisor for generating I2S clock frequency. The selected clock with CLOCK_SEL is divided by this. ‘0’: Bypass ‘1’: 2 x ‘2’: 3 x ‘3’: 4 x … ‘62’: 63 x ‘63’: 64 x
CLOCK_SEL

Selects clock to be used by I2S: ‘0’: Internal clock (‘clk_audio_i2s’) ‘1’: External clock (‘clk_i2s_if’)

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data